With the increasing levels of integration in today's integrated circuits and ever-increasing digital circuit speeds, the problem of substrate noise is more and more pronounced. The performance of sensitive analog circuits can be severely degraded by excessive substrate noise. The effect of substrate noise on the circuits within an IC is typically observed during the testing phase only after the chip has been fabricated. However, this is often too late, for if the substrate noise negatively impacts the performance of the circuit, the circuit must be laid out again and re-fabricated. This consumes valuable time and money. Therefore, a determination of substrate noise coupling during the design phase would be extremely beneficial to circuit designers who can incorporate the effect of the noise and re-design accordingly before fabrication. This would reduce the turn around time for circuits and prevent costly redesign.
Work in the area of pre-fabrication substrate noise modeling and analysis falls into several categories. The first is the simulation of digital circuits to determine the substrate noise generated. To be able to manage the substrate noise problem, the need for simulation to predict substrate noise performance is becoming more evident.
Standard techniques to simulate expected substrate noise tend to be either accurate but extremely inefficient, or fast but rather inaccurate. Noise macromodelling approaches fall in between these two ends of the spectrum. The inefficient techniques are accurate because all noise sources, coupling, and propagation mechanisms are well modeled; however, this leads to a large number of nodes in the simulation model. This excessive number of nodes accounts for the temporal inefficiency. These techniques involve simulating a large number of nonlinear devices in order to accurately model the noise current profiles. In contrast, the fast techniques rely on the random nature of the noise generated. These techniques assume that if the number of gates is large enough and if the global switching activity is uniformly distributed over a large portion of the spectrum, the noise can be modeled as a single Gaussian white or pink noise source. Approximating the noise as a Gaussian source captures only a small portion of the entire energy spectrum. Thus, detrimental noise components are often omitted or grossly underestimated.
The second category concerns modeling the substrate itself. Most work on substrate noise falls into this category. Different approaches to accurately model the substrate typically result in an extremely large mesh of passives. Much work has focused on techniques to reduce the substrate netlist to a more manageable form while maintaining accuracy. Accurate substrate modeling is a very complex problem. However, more rudimentary substrate models were developed to permit extremely fast substrate simulations at the expense of some accuracy.
The final category of work and also the least developed is in the area of examining the effect of substrate noise on analog circuits. Most of the efforts have focused on low frequency circuits such as A/D converters. Most work on radio frequency (RF) circuits has been limited to low noise amplifiers. There are at least two existing approaches to substrate noise simulation. The first is a full transistor level methodology to simulate for substrate noise. As described above, this approach yields the most accurate data, however it can be both time and computation intensive. The second approach uses noise macromodels to decrease the time required to perform the simulation.
FIG. 1(a) shows the cross-section of an NMOS device 100 and the elements that are added to model injection into the substrate. The traditional NMOS device 100 comprises a drain region 101 and a source region 102; implanted into a substrate 103. These source and drain regions are capacitively coupled to the substrate 103 through the depletion capacitances 104. These nonlinear capacitances depend on the source and drain voltages, according to the following equation:Cj=ACJA/(1−V/ΦB)mA+PCJSW/(1−V/ΦB)mSW  (1)Where    A=Area    CJA=Zero bias area junction capacitance    V=Bias across junction    ΦB=Junction potential    MA=Area Grading Coefficient    P=Perimeter    CJSW=Zero bias sidewall junction capacitance    and mSW=Sidewall Grading Coefficient
Because of this dependence on voltage, these capacitances will vary over time if the outputs are switching.
The bulk node 105 of the device is resistively connected to the local substrate node through a resistance 106 given by the equation given below. ρ is the resistivity of the channel region. For an epi substrate, T is the thickness of the epi layer. For a non-epi substrate, T is roughly the junction depth. L and W correspond to the junction's length and width, respectively.Rbulk=ρT/LW  (2)
The final element that is added to account for coupling into the substrate 103 is the resistance of the substrate contact 107, which is connected to ground through a bond wire. A series resistance 108 and inductance 109 is used to model the bond wire impedance. The amount of noise that couples through the substrate contact 107 can be quite significant. Typically the source 102 is shorted to the substrate contact to prevent any threshold voltage fluctuation. In doing so, switching currents work in tandem with the impedance associated with the ground line to create ground bounce. This node is resistively connected to the substrate resulting in most of the ground bounce appearing on the substrate itself.
FIG. 1(b) shows all of these passive elements introduced in the circuit. Therefore, to properly model injection into the substrate, these four additional elements (source depletion capacitance 104b, drain depletion capacitance 104a, the bulk resistance 106 and the substrate contact resistance 107) must be added to each NMOS device. In most circuits, a simplification is possible, since the source is connected to the same ground as the substrate contact 107 thus shorting out the source depletion capacitance 104b. In this case, only three additional elements need to be added to each NMOS device.
FIG. 2(a) shows the cross-section of a PMOS device 200 and the elements that are added to model injection into the substrate. The elements that must be added to a PMOS device 200 are similar to those added to an NMOS device 100, except an additional term to model the n-well 210 must be incorporated. All elements of the PMOS device 200 that are equivalent to the NMOS device 100 are shown with similar reference designators. Specifically, the two lower digits of the reference designator are the same. Thus, the bulk resistance of the NMOS device is designated as 106, while the bulk resistance of the PMOS device is designated as 206. These additional elements are shown in FIGS. 2(a) and 2(b).
The expression for the depletion capacitance 204 is roughly the same, except signs are changed to compensate for the PMOS nature. The expression for Rbulk 206 is given in equation (2) is the same for the PMOS device 200 except the resistivity is now the resistivity of the n-well 210. The substrate contact 207 for the PMOS is connected to VDD through bondwires. The local substrate node 205, however, is shielded from the substrate by the n-well 210. This is modeled with a resistance 206 through the n-well 210 and a capacitance 211 representing the n-well junction capacitance.
For each PMOS device, six additional elements are required to model noise injection into the substrate. However, for most circuits, the source 202 is connected to the same power supply as the substrate contact 207, thereby shorting out the depletion capacitance 204b. This results in only five additional elements needed to model the injection for a PMOS device.
The following example is used to illustrate the complexity of this approach. FIG. 3 shows the equivalent circuit for a single CMOS inverter, including the additional passive components needed to model the substrate noise. Similar reference numbers are used to correspond to elements illustrated in FIGS. 1 and 2.
To predict the noise injected by a single CMOS inverter, the elements described above need to be added to the inverter circuit to account for injection into the substrate. The circuit in the dashed box 300 of FIG. 3 represents the inverter with the additional elements to model injection into the substrate, as described in conjunction with FIGS. 1 and 2. For such a simple circuit, an additional eight nodes (located within dashed box 300) have to be simulated with a combination of nonlinear and linear devices to determine the noise injected into the substrate.
The circuit elements in dashed box 301 represent the model for the substrate at low frequencies. Additional nodes have to be simulated in order to model propagation in the substrate. For example, resistors 302 through 309 are added to represent the resistance through the substrate. This resistor network is obviously dependent on the physical size of the substrate, as well as the number of elements in the circuit. From this simple example, it is apparent that the additional elements that have to be added to model for substrate noise increase rapidly with the size of the circuit.
The circuit in dashed box 310 is the model for a substrate contact used to probe the substrate noise.
Consider a medium-scale circuit with approximately one million devices. Based on the simple example shown above, to model injection into the substrate, an additional four million passive elements must be added to the circuit. Thus, in order to predict the noise injected, a simulation of one million nonlinear devices and four million passive elements has to be performed. To properly model propagation within the substrate itself, yet more elements must be added. Because the complexity of the circuit scales rapidly with circuit size, the simulation time will be excessively long and in many cases will not converge.
As described above, transistor level simulation techniques result in prohibitively long simulation times. If the noise behavior could be abstracted to a higher level while still preserving the relationship to the substrate, simulation times could be reduced. One way of accomplishing this is to extract the switching behavior of the digital circuit and to use mathematical models to calculate the substrate noise. In one embodiment, a behavioral model based on a modeling tool, such as AnalogHDL, is used. Switching transitions from the modeling tool, such as AnalogHDL, together with mathematical expressions for the substrate noise are used to predict the substrate noise profile. Because mathematical expressions instead of real waveforms are used to generate the noise profiles, this methodology yields less accurate predictions of the substrate noise. Furthermore, with technology scaling, mathematical models used to model transistor behavior are becoming more complex. Because this technique relies on the ability of the mathematical expressions to model the substrate noise behavior, its accuracy will further diminish for future technology nodes.
Another technique that abstracts the noise behavior is macromodelling. In order for the macromodels to still yield accurate results, the noise behavior of the circuit has to be completely encapsulated. This involves not only accurately modeling injection into the substrate but also accurately modeling the switching noise.
Noise macromodelling approaches fall into two categories. Several of these methodologies are input dependent and follow a similar flow. These approaches are based on the superposition of patterns and current profiles to generate the noise signature. Noise waveforms at critical nodes are determined based on user-supplied I/O vectors. Switching elements are typically simplified using linear macromodels that mimic the switching behavior of the original circuit. These techniques generate an equivalent circuit similar to that shown in FIG. 4. Each, however, uses a different noise macromodel.
These approaches yield very good accuracy with reasonable simulation times. The main limitation of the macromodelling technique is that determining the worst case noise behavior of the circuit can be a formidable task. Multiple simulations over different input conditions have to be performed.
Substrate noise analysis has also been done using input independent simulation. One such methodology relies on power dissipation data from a system-level power estimator to predict the substrate noise profile. In that embodiment, substrate coupling from interconnects and source/drain diffusion regions were assumed to be negligible compared to VDD and ground noise. More and more digital systems are interconnect dominated, and in such circuits, the noise contribution from interconnect can be significant. However, this assumption was valid for small scale circuits where the role of the interconnect was not important. Because only power supply noise was considered, examining the power dissipation permitted the prediction of current transients that dissipated the power. This methodology determined RMS contours of the substrate noise that represent the average amount of noise at any point on the substrate. This technique cannot be used to examine the time varying nature of the substrate noise or to determine the frequency content of the noise. Knowing only an estimate of the peak substrate noise value without knowing its frequency content is not entirely useful. The purpose of determining the noise profile is to be able to design appropriate isolation structures and to determine the effect of that noise on any analog circuits that are integrated with the digital system. For example, if a narrowband RF circuit is to be integrated with a particular digital system, only the noise generated in band is of interest. Without knowing the frequency content, the severity of the substrate noise problem cannot be assessed. Furthermore, the amount of attenuation afforded by isolation structures is frequency dependent. Without knowing what frequencies should be targeted, the isolation structure design will not be optimized. Therefore, this technique can only be used to generate a rough estimate of the noise and thus is most useful for floorplanning.
In summary, each of the methodologies used in the prior art has at least one shortcoming that impacts its effectiveness. A full SPICE transistor level simulation yields the most accurate results; however, it is impractical for most circuits as the run-time increases rapidly with circuit complexity. For typical circuits, full transistor level simulations require several weeks to simulate a few clock cycles and often do not converge. Approaches that employ macromodels are also known in the prior art and significantly reduce simulation time. However, each macromodel approach has its own shortcomings. The most common problem is that the noise macromodel does not completely encapsulate the noise behavior of the original circuit. Furthermore, certain assumptions inherent in specific tools do not permit the tool for use with non-epi substrates. With technology scaling, latch-up is becoming less of a concern; thus, non-epi substrates are becoming more prevalent for their improved noise isolation properties over epi substrates. Several other prior art methodologies use a substrate model generated by SubstrateStorm, a tool available from Cadence. SubstrateStorm requires a full layout of the circuit with a substrate doping profile. Because a full layout is required, substrate noise simulation can only be performed at the end of the design cycle.
Furthermore, there exist several tools that can be used to predict the substrate noise profile of digital systems. However, none of these are flexible enough to work at any stage in the design cycle. Specifically, these tools can only be used for final verification. Final verification of the substrate noise performance of a digital system is an important part of substrate coupling analysis. However, a tool that can yield information at earlier stages in the design cycle permits changes in both the design and the layout to try to mitigate noise coupling and, thus, performs a much more valuable function. Such a tool should be able to work at higher abstraction levels to tradeoff accuracy for simulation speed. Additionally, the tool should be able to work at various granularity levels to tradeoff simulation speed for accuracy. This would allow the tool to be useful during various stages of IC design.